1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device having reduced power consumption.
2. Description of the Prior Art
As is well known, a semiconductor memory device includes a plurality of memory cells arranged in a matrix form, a decoder circuit, a multiplexer circuit, a group of word lines connected to the decoder circuit to activate one of the rows of the matrix, and a group of bit lines connected to the multiplexer circuit to activate one of the columns of the matrix. When a memory system requires a memory capacity over that of a single memory device, two or more memory devices are provided in parallel.
The conventional technique for reducing power consumption of a memory system is to provide a switching circuit outside each memory device. The switching circuit is connected to the power supply terminal of the memory device. Using the switching circuit, it is possible to supply power only to the memory device which is to be accessed, i.e., power is not supplied to other memory devices.
This method, however, is disadvantageous in that the switching time for the switching circuit outside of the memory device increases in memory access time.
Also, this method is rapidly losing its effectiveness in the face of the recent increases in memory capacities of individual memory devices, now 64K bits or 128K bits, which result in increases in the size of the memory devices. It is no longer sufficient to reduce the power consumption of the memory device by switching off power to nonaccessed memory circuits.